1. Field of the Invention
The present invention relates to electrically erasable and programmable memories in integrated circuits, and more particularly the testing of these memories prior to marketing.
The present invention also relates to the implementation of a so-called “blank verify” or erase verify test, in serial input/output Flash memories.
2. Description of the Related Art
The testing of an electrically erasable and programmable memory integrated onto a micro-wafer of silicon is an essential step allowing integrated circuits having manufacturing defects to be detected.
Out of the various tests known, the erase verify test allows manufacturing defects such as short-circuits due to residual filaments of metal or polycrystalline silicon deposited unintentionally on the surface of the integrated circuits to be detected.
This test is generally applied to all the pages of a memory and comprises, for each page, the following steps:                complete erasure of the page,        programming the page word by word, and verifying before each word is programmed that the programming of the adjacent word has not affected the memory cells to be programmed,        rejection of the memory if one memory cell presumed to be in the erased state contains a bit the logic value of which corresponds to the programmed state.        
This test is illustrated on FIGS. 1A, 1B, 1C. On FIG. 1A, a page of a memory containing words of 8 bits or bytes has been entirely erased and thus only comprises words equal to 1 (the logic 1 being considered here and in the description below as the erase logic value, i.e. the logic value contained in a memory cell in the erased state). On FIG. 1B, the first word W0 of the page has been set to 0 which corresponds to an operation of programming all the memory cells containing the bits of the word W0. The adjacent word W1 or second byte of the page only comprises 1s, as well as the following bytes of the page, such that no defect is noticed. FIG. 1C represents a case of failure of the erase verify test. After programming the nth word Wn of the page, the following word Wn+1 is read and comprises the byte “01111111” instead of the byte “11111111”. That means that a short-circuit has led to the unintentional programming of the first memory cell of the word Wn+1 during the programming of the word Wn (or of another word, although the short-circuits generally occur between adjacent memory cells). A memory having this type of malfunction is thus rejected.
On a parallel input/output Flash memory PMEM, of the type represented in FIG. 2A, the implementation of this test does not present any particular difficulty. The memory PMEM comprises a parallel address input ADIN, parallel data inputs/outputs DTIO, an input for receiving a write command WRITE, an input for receiving a read command READ, and a select input CHSEL. After erasing a page, the erase verify test sequence is done word by word and comprises the addressing of the target word, the reading of the target word to check that this word only comprises 1s, then the setting to 0 of the word (programming all the corresponding memory cells).
On the other hand, on a serial input/output Flash memory SMEM, of the type represented in FIG. 2B, the implementation of this test has the disadvantage of requiring a quite considerable amount of time. This memory only comprises one serial input for receiving data DTIN, one serial output for sending data DTOUT, and one select input CHSEL. The application of a read command requires the application bit by bit to the serial input of a code of the operation to be performed, of the address of the word to be read, i.e. in general at least 4 bytes (1 command byte and 3 address bytes), then the reading bit by bit of the word at the output DTOUT. The same applies to the writing of a word, which requires the application bit by bit of the value of the word to be written.
Thus, an erase verify test takes a long time to implement on a serial Flash memory and increases the cost prices of the serial memories by slowing down production rates, the test steps being part of the manufacturing process.